2)Assume we are using 2-way set associative mapping with a main memory of 1MB and a cache that holds 1KB. Each cache block contains 32 bytes and cache is initially empty.
- Complete the table below. (You must use hexadecimal numbers for all answers.)
- Does any of the addresses cause a collision? If your answer is either yes or not, you must clearly explain why?
|Address||Tag||Cache Location (Set)||Offset|
3)Given the following sequence of instructions:
LDUR R1, [R4, #100]
AND R8, R1, R3
CBZ R2, Label
SUB R10, R1, R7
Assuming the register file can be read and written in the same cycle and there is a single memory unit
- Outline pipeline stages for each instruction (per cycle) (you can create a table for this) and number of cycles it takes to complete this sequence.
- Identify if there are any hazards or not. If any hazard, explain the type of hazard and how could be fixed?
4)Suppose we have a memory system with a virtual address space of 28 bytes and physical memory of 4 page frames where each page is 32 bytes in length:
- How many bits does each virtual address have? Show your work.
- How many bits does each physical address have? Show your work.
- Each virtual address is divided into two fields: the page field and the offset field. How many bits are allocated for the page field and how many bits are allocated for the offset field? Show your work.